As apparatuses to record a video signal on a recording medium as a digital signal, a so-called digital still camera which records a video image of object as a still picture on a memory device or disk, a combination camera and digital video tape recorder as a video tape recorder which digital-records a video image of object as a moving picture by using a magnetic tape, and the like, are practically used.
For example, the conventional combination camera and digital video tape recorder comprises an image sensing unit having a lens system which forms an image from incident light passed through a lens and a solid image sensing device such as a CCD which photoelectric-converts the incident light from the lens system into an electric signal, a camera signal processor which inputs an output signal from the image sensing device and performs signal processing in the camera, a VTR signal processor which inputs a digital video signal from the camera signal processor and performs VTR signal processing on the signal, a recording and reproduction system which records an output digital signal from the VTR signal processor on a magnetic tape upon recording and reproduces information recorded on the magnetic tape upon reproduction, and a control system which controls the lens system, the solid image sensing device, the camera signal processor, the VTR signal processor and the recording and reproduction system.
In a case where the solid image sensing device is a generally-used chrominance line-sequential complementary-color interline type CCD, the camera signal processor inputs a video signal outputted form the image sensing device into a correlated double sampling (CDS) circuit. The video signal outputted from the CDS circuit is inputted into an automatic gain control (AGC) circuit then A/D converted by an A/D converter into a digital signal, and inputted into a digital signal processing (DSP) circuit. The DSP circuit performs predetermined digital signal processing on the signal, and obtains a luminance signal component Y. Further, after synchronization of the color signals, the DSP obtains chrominance signals Cr(=R-Y) and Cb (=B-Y) and outputs the signals. Further, white balance control and AGC control to gain-control the signal level of the video signal are performed in accordance with control signals from the control system.
The VTR signal processor outputs a video signal, from the digital video signal from the camera signal processor, via an output terminal. The VTR signal processor is supplied with a control signal to generate a digital VTR signal corresponding to the digital recording format of the VTR from the control system. The digital recording format will be described later.
Upon recording, the recording and reproduction system records the video signal supplied from the VTR signal processor, as a moving picture or still picture, in a digital signal format, on a recording track of magnetic tape, via a rotary magnetic head provided in a rotary head drum. Further, upon reproduction, the recording and reproduction system reproduces the digital video signal recorded on the recording track of the magnetic tape, as a moving picture or still picture, via the rotary head drum.
FIG. 8 shows an example of circuit to generate pulses of synchronizing signals and control signal pulses outputted from the control system for adjusting operation timing of the entire apparatus. In FIG. 8, a clock generated by a reference clock generator 801 is inputted into a horizontal pulse counter 802 and a horizontal latch circuit 803. When the clock is inputted into the horizontal pulse counter 802, the counter output changes in correspondence with the number of clocks, and address data of horizontal pulse ROM 804 changes. The horizontal pulse ROM 804 holds data on control pulses necessary to control the lens system, the solid image sensing device, the camera signal processor, the VTR signal processor and the recording and reproduction system. The data outputted from the horizontal pulse ROM 804 also changes in accordance with the change of address, then the data is latched by the latch circuit 803, and pulses in a horizontal direction, i.e., a horizontal synchronizing signal such as HD, an image-sensing device horizontal drive control pulse, a horizontal control pulse and the like, are outputted. Similarly, regarding a vertical direction, the horizontal synchronizing signal such as HD from the horizontal latch circuit 803 is counted, and pulses in the vertical direction, i.e., a vertical synchronizing signal such as VD, an image-sensing device vertical drive control pulse, a vertical control pulse and the like, are outputted.
The digital video signal processing circuit (DSP) in the camera signal processor and the VTR signal processor is also supplied with the reference clock. In accordance with the synchronizing signals HD, VD and the control signal pulse outputted from the control system in synchronization with the reference clock, calculation processing is performed on a digital video signal, and the digital video signal data is latched and transmitted in synchronization with the reference clock. In this arrangement, the respective circuit systems start operations and perform processing.
As the digital recording format video signal outputted from the above-described VTR signal processor is a formatted parallel bus signal, it can be outputted via an external terminal and subjected to computer image processing in addition to the case where the signal is outputted to the recording and reproduction system incorporated in the apparatus.
Generally the VTR signal processor is an IC made by a system LSI manufacturing method as a combination of cell libraries having macrocells with various circuit functions made by a gate array process. Upon formation of the IC VTR signal processor to satisfy the above specification and to accurately transmit a digital signal to the incorporated recording and reproduction system, generally a drive cell having a higher current drive performance in comparison with other circuits is used as a parallel bus drive circuit which is further added to an output final stage of the VTR signal processor.
FIG. 9 shows an example of arrangement of the processing final stage and the parallel bus drive circuit in the conventional VTR signal processor.
A digital recording format video signal outputted from a VTR signal processor 104 is converted based on e.g. a format as shown in FIG. 4. FIG. 4 shows the outline of 8-bit parallel signal in CCIR Rec 601(consumer digital camcoder digital signal format) which is a typical digital recording format. In the digital signal format, 4-word data is added to start point and end point of H blanking period. FIG. 5 shows the contents of the additional data (EAV and SAV).
As shown in FIG. 5, bits from 1 to 0 exist in the additional data, and as all the bit change in the same phase, the transition potential becomes maximum.
However, as the data arrangement of H blanking and image data portion other than the additional data is point-sequential Cb, Y1, Cr, Y2, respective bits change differently. Accordingly, changes in the same and reverse phases and unchange are integrated to always a small amount, and as a result, the transition potential of the image data portion is small.
Accordingly, as the parallel bus drive circuit added to the output final stage of the VTR signal processor uses a drive cell having a current drive performance higher than other circuits, a high shot circuit current flows through the power supply and the ground of the parallel bus drive circuit only in a transition point of the change bit, which cannot avoid occurrence of noise which appears as a voltage variation due to common impedance component to the other circuits. In a case where the noise component is mixed into the CDS circuit when the AGC gain is high, the change may cause vertical-stripe fixed pattern noise.
FIG. 7 is a timing chart showing timings of the parallel bus drive circuit output and CDS circuit operation in the case where fixed pattern noise occurs. In FIG. 7, reference numeral 701 denotes a reference clock. Numeral 702 denotes an example of point-sequential data arrangement on parallel bus, i.e., time array of one of 8-bit parallel bus signals. Numeral 703 denotes an EAV portion of data arrangement in the H blanking portion of the data arrangement 702. A 4-bit part indicated with an arrow is the EAV constructing 4 words with other 7 bus signals (not shown). Similarly, numeral 704 denotes an SAV portion of data arrangement in the H blanking portion of the arrangement 702. A 4-bit part indicated with an arrow is SAV constructing 4 words with the other 7 bus signals (not shown). Numeral 705 denotes an example of noise component occurred in each bit transition point in the data array 704. The noise occurred at the rising edge and that falling edge of the first word of SAV are larger than those in other bits. Numeral 706 denotes a waveform schematically showing an image sensing video signal outputted from the solid image sensing device, where alphabet A represents a reset period, B, a feed through period at a reference level, and C, a photoelectric-conversion signal output period. The image sensing video signal is outputted in repetition of periods A, B and C as one cycle. Note that in FIG. 7, the drive cycle of the solid image sensing device is double of the cycle of the reference clock 701.
Further, in FIG. 7, numeral 707 denotes a phase pulse for sampling the feedthrough period B when the image sensing video signal 706 outputted from the solid image-sensing device is inputted into the CDS circuit and processed there, and 708, a phase pulse for sampling the photoelectric-conversion signal in the period C. The phases and opening lengths of these sampling pulses are set in most appropriate positions to obtain effect of the CDS circuit (generally noise suppression effect to 4 to 5 dB reset noise and output amplifier noise) and uniquely determined. In the waveform 706, the noise component 705 is mixed with the image sensing video signal at timing D.
FIG. 6 schematically shows the video signal output where the noise is mixed. In FIG. 6, numeral 601 denotes an image signal position upon image-sensing device signal output, where a hatched portion represents an effective video signal region including optical block bit array provided on an image sensing device photoelectric conversion region.
Numeral 602 denotes an image signal position upon parallel bus drive circuit output, where a hatched portion represents H blanking and V blanking positions. The image signal position 602 is delayed in a horizontal direction from the image signal position 601 mainly by time for processing by repeatedly performing calculation and data latch on the digital video signal in the camera signal processing and VTR signal processing, with respect to a horizontal reference position HD.
The processing time differs in accordance with processing content. In use of the above-described general-purpose chrominance line-sequential complementary-color interline type solid image sensing device, in digital video signal processing in the camera signal processor and the VTR signal processor and the like, generally an about 100 clock delay occurs. Note that regarding a line delay in a vertical direction due to synchronization processing in the vertical direction using a 1-horizontal-line memory or the like, since the direction of the delay is different from that of the horizontal delay, the vertical delay is not considered here. In a case where the number of clocks corresponding to one horizontal period is about 1700 clocks (27 MHz), the 100 clock delay is approximately 1/17.
In FIG. 6, noise which occurred in a particular bit position in the image signal upon parallel bus drive circuit output, assuming that the processing time is about 1/17 of the horizontal synchronizing period, is mixed into image signal upon image-sensing device signal output, and the noise appears as fixed pattern noise in a position delayed in the horizontal direction by the processing time.
To avoid the mixing of noise, an IC chip having the functions of the above-described analog signal processors, the image sensing device, the CDS, the AGC and the A/D, and an IC chip having the functions of the VTR signal processor as a DSPIC including the parallel bus drive circuit are arranged in careful consideration of isolation state between the power supply and the ground circuit, the packaging position, circuit pattern traces and the like in each IC chip.
In recent IC manufacturing techniques, fine circuit patterns are developed, and 1 chip has various functions. For example, an IC where the functions of the above-described CDS, AGC and A/D are integrated is known. A DSPIC where camera signal processing and VTR signal processing are combined is already well-known. As these two IC's can be manufactured by the same CMOS process, a large-scale IC where these IC's are integrated in 1 chip, to directly input an image sensing video signal from an image sensing device and directly output a digital recording format video signal, will appear in the future.
In this case, even if the circuit arrangement and isolation between the power supply and the ground circuit are fully considered, as the analog signal processors, the CDS, the AGC and the A/D, the VTR signal processor, and the parallel bus drive circuit are positioned in proximity to each other, the above-described mixing of noise cannot be prevented.
Accordingly, means for preventing the above-described mixing of noise is required to realize a so-called 1 chip signal processing IC where the analog signal processors, the CDS, the AGC and the A/D, the VTR signal processor, and the parallel bus drive circuit are integrated.